1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method of the same, and more particularly to a stacked type flash memory and a manufacturing method of the same.
2. Description of the Related Art
Conventionally, among nonvolatile semiconductor memory devices capable of performing electrical rewriting, flash memories which have functions for electrically erasing a plurality of memory cells in a required region in a flush have been available. Among these flash memories, there is one, which is composed of stacked gate type memory cells.
FIG. 1 is a typical plan view showing one construction example of a conventional flash memory composed of stacked gate type memory cells. FIG. 2(a) is a section view taken along the line X-X' of the flash memory shown in FIG. 1, and FIG. 2(b) is a section view taken along the line Y-Y' of the flash memory shown in FIG. 1.
Referring to FIGS. 1 and 2(a), on the surface of a P type silicon substrate 201, there are provided a field oxide 202 in an element isolation region and stacked gate type memory cells in an element formation region. Each of the memory cells is composed of a gate oxide film 210 provided on the surface of the P type silicon substrate 201, a floating gate electrode 215 formed of an N type polycrystalline silicon film, which is provided on the surface of the P type silicon substrate 201 via the gate oxide film 210, a gate insulating film 213 formed by stacking a silicon oxide film, a silicon nitride film and a silicon oxide film, which is provided on the surface of the floating gate electrode 215, a control gate electrode 216 formed of an N+ type polycrystalline silicon film as a word line, which is formed on the floating gate electrode 215 via the gate insulting film 213, and a source region 208 and drain regions 207a and 207b formed on the surface of the P type silicon substrate 201. Each floating gate electrode 215 belongs to each memory cell.
The source region 208 and the drain regions 207a and 207b are formed of N+ type diffusion layers, each of which is formed in self alignment with, for instance, a nitride film pattern 205. The drain regions 207a and 207b are connected to bit lines 219a and 219b formed on the surface of an interlayer insulating film 217 through contact holes 218, which are provided at each interval of 16 memory cells in the interlayer insulating film 217 covering the memory cells. The source region 208 is shared by a required number of memory cells, and as in the case of the drain regions 207a and 207b, each source region 208 is connected through the contact hole 218 to a source line 220, which is formed on the surface of the interlayer insulating film 217.
In the flash memory of this type constituted as above, N+ type diffusion layers are used as sub-bit and sub-source lines. Instead of one contact hole provided for one memory cell, drain and source regions composed of the N+ type diffusion layers are shared. For a plurality of memory cells, one contact hole exists in the drain region and one in the source region. The existence of one contact hole for the plurality of memory cells makes it possible to reduce the areas of the memory cells and is thus effective for the reduction of a chip size. The memory cell construction described above is referred to as a buried diffusion layer type flash memory, hereinafter.
Data writing and erasing operations for the above-noted buried diffusion layer type flash memory are summarized as follows with a voltage applied to the drain regions 207a and 207b, a voltage applied to the source region 208, a voltage applied to the control gate electrode 216 and a voltage applied to the P type silicon substrate 201 respectively set to V.sub.DD, V.sub.SS, V.sub.CG and V.sub.SUB.
Memory cell writing implies pulling out of electrons injected into the floating gate electrode 215 therefrom. For example, writing is performed by respectively applying V.sub.CG =-9V to the control gate electrode 216 which belongs to a memory cell targeted for writing, V.sub.DD =5V to the drain regions 207a and 207b and V.sub.SUB =0V to the P type silicon substrate 201 and opening the source region 208. During this period, in the control gate electrode 216 selected for writing and the memory cell which belongs to the drain region 207, an electric field applied to the gate oxide film 210 is higher than those of the other memory cells. Consequently, a Fowler-Noldheim current (referred to as a FN current, hereinafter) based on a quantum tunnel effect flows, and thus electrons are pulled out of the floating gate electrode 215 of this memory cell. A threshold voltage of the memory cell is shifted in a negative direction and reduced from about 5V to about 2V.
Erasing of the memory cell is performed by injecting electrons into the floating gate electrode 215. Erasing in the flash memory is performed for each memory array. For example, erasing is performed by respectively applying V.sub.CG =16V to the control gate electrode 216, V.sub.DD =0V to the drain region 207, V.sub.SUB =0V to the P type silicon substrate 201 and V.sub.SS =0V to the source region 208. Thus, a high electric field is applied to each gate oxide film 210 of all the memory cells which belong to the control gate electrode 216. Consequently, an FN current based on the quantum tunnel effect flows as in the case of writing and accordingly electrons are injected into the floating gate electrode 215 of this memory cell. A threshold voltage of the memory cell is shifted in a positive direction and increased from about 2V to about 5V.
A manufacturing method of the flash memory constructed in the above-noted manner will be described below.
FIGS. 3 to 13 are typical plan views each illustrating a manufacturing method of the flash memory shown in FIG. 2.
First, a field oxide 202 is formed in the element isolation region of the surface of the P type silicon substrate 201. Subsequently, a first oxide film 203 having a thickness of 4 nm is formed and then a nitride film 204 having a thickness of about 300 nm is grown on the full surface (FIG. 3).
Then, the nitride film 204 is patterned in a striped form and a nitride film pattern 205 is formed. Thereafter, by using the nitride film pattern 205 as a mask, arsenic ions of 5E15 cm-2 are implanted at 70 KeV approximately in parallel with a normal on the surface of the P type silicon substrate 201, and an arsenic ion implanted layer 206 is formed in the P type silicon substrate 201 (FIG. 4).
Then, the arsenic ion implanted layer is subjected to a heat treatment in a nitrogen atmosphere of 850.degree. C. for 30 minutes. By this heat treatment, the arsenic ion implanted layer 206 is activated and drain regions 207a and 207b and a source region 208 composed of N+ diffusion layers are formed (FIG. 5).
Then, by performing thermal oxidation at a temperature of 850.degree. C., second oxide films 209a, 209b and 209c each having a thickness of about 100 nm are formed on the drain regions 207a and 207b and the source region 208 (FIG. 6).
Then, the nitride film pattern 205 and the first oxide film.203 are removed in sequence by etching, and a portion of the surface of the P type silicon substrate 201 is exposed (FIG. 7).
Then, a gate oxide film 210 having a thickness of about 8 nm is formed in the element formation region of the surface of the P type silicon substrate 201 by thermal oxidation, and thereafter a first N type polycrystalline silicon film 211 is formed on the entire surface (FIG. 8).
Then, the first polycrystalline silicon film 211 is patterned on a stripe-like polycrystalline silicon film 212 so as to be in parallel with the bit line (FIG. 9).
Then, a gate insulating film 213 is formed on the entire surface (FIG. 10).
Then, a second N+ type polycrystalline silicon film 214 is formed on the entire surface (FIG. 11).
Then, the second polycrystalline silicon film 214, the gate insulating film 213 and the polycrystalline silicon film pattern 212 are sequentially patterned, and thereby a control gate electrode 216 composed of the second polycrystalline silicon film 214 and a floating gate electrode 215 composed of the polycrystalline silicon film pattern 212 are formed. Subsequently, by thermal oxidation, silicon oxide films (not shown) each having a thickness of 10 to 20 nm are formed in the exposed surfaces of the control gate electrode 216 and the floating gate electrode 215 and the surface of the P type silicon substrate 201 (FIG. 12).
Then, an interlayer insulating film 217 formed of a BPSG film having a thickness of about 0.8 .mu.m is formed on the entire surface, and subsequently a contact hole 218, and so on, reaching-the drain regions 207a and 207b and the source region 208 are formed. An area of the bit contact hole 218 is 0.4 .mu.m.sup.2. Thereafter, an aluminum metallic film having a thickness of about 0.45 .mu.m is formed on the entire surface. By patterning this metallic film, bit lines 219a, 219b, a source line 220, and so on, are formed (FIG. 13).
However, in the conventional flash memory described above, because the drain regions and the source region cannot be formed in self alignment with the polycrystallinefilms, its manufacturing process becomes long and micro fabrication of memory cells is difficult.
In the conventional manufacturing method described above, first, the drain regions and the source region were formed in self alignment with the nitride film pattern, and then when the width of the nitride film pattern was set to, for instance 0.4 .mu.m, the capacitance ratio of the memory cell was set to, for instance about 0.7 by greatly increasing the width of the polycrystalline silicon film pattern to, for instance 1.45 .mu.m.
The capacitance ratio of the memory cell will be described below.
The memory cell capacitance ratio is an important parameter for the operations of the memory cell, which includes writing, erasing and reading operations. The capacitance ratio is defined by the following formula. EQU Vfg=.alpha.(Vcg-.DELTA.Vth) EQU .alpha.=Cfg/Ct
Herein,
Vfg: Potential of floating gate electrode PA1 Vcg: potential of control gate electrode PA1 .alpha.: Capacitance ratio PA1 .DELTA.Vth: Shifting amount of memory cell threshold voltage PA1 Cfg: Capacitance between floating gate electrode and control gate electrode PA1 Ct: Capacitance of all around floating gate electrode PA1 a floating gate electrode provided on the surface of a semiconductor substrate through a gate oxide film; PA1 a control gate electrode provided on the surface of the floating gate electrode interposing a gate insulating film and functions also as a word line; PA1 a drain region provided on the surface of the semiconductor substrate, the drain region being connected to a bit line composed of an N+ type diffusion layer orthogonally crossing the word line; and PA1 a source region provided on the surface of the semiconductor substrate, the source region being connected to a source line composed of an N+ type diffusion layer orthogonally crossing the word line. PA1 forming a gate oxide film in an element formation region of a semiconductor substrate surface by thermal oxidation; PA1 forming an N type polycrystalline silicon film of a predetermined impurity concentration on the entire surface of the semiconductor substrate, the N type polycrystalline silicon film having projecting and recessing parts in an upper surface thereof; PA1 forming a gate insulating film on the entire surface of the semiconductor substrate; PA1 forming a predetermined polycrystalline silicon film pattern by sequentially patterning the gate insulating film and the polycrystalline silicon film using a first photoresist film pattern as a mask; PA1 forming an arsenic ion implanted layer by implanting arsenic ions in parallel with a normal to the surface of the semiconductor substrate with the first photoresist film pattern used as a mask; PA1 forming drain and source regions composed of N+ type diffusion layers on a surface of the semiconductor substrate by removing the first photoresist film pattern and performing a heat treatment at a specified temperature so as to activate the arsenic ion implanted layer; PA1 forming oxide films on the drain and source regions in the surface of the semiconductor substrate by thermal oxidation; PA1 forming a control gate electrode composed of a conductive film and a floating gate electrode composed of the polycrystalline silicon film pattern by forming a conductive film on the entire surface of the semiconductor substrate and sequentially patterning the conductive film, the gate insulating film and the polycrystalline silicon film pattern; and PA1 forming an interlayer insulating film on the entire surface of the semiconductor substrate, a contact hole reaching the N+ type diffusion layer in the interlayer insulating film and bit and source lines respectively connected to the drain and source regions interposing the contact hole on the surface of the interlayer insulating film. PA1 a floating gate electrode provided on a surface of a semiconductor substrate through a gate oxide film; PA1 a control gate electrode provided on a surface of the floating gate electrode through a gate insulating film, the control gate serving also as a word line; PA1 a drain region provided on the surface of the semiconductor substrate, the drain region being connected to a bit line composed of an N+ type diffusion layer orthogonally crossing the word line; PA1 a source region provided on the surface of the semiconductor substrate, the source region being connected to a source line composed of an N+ type diffusion layer orthogonally crossing the word line; and PA1 a side wall oxide film formed on a side face of the floating gate electrode and above the drain and source regions. PA1 forming a gate oxide film in an element formation region of a semiconductor substrate surface by thermal oxidation; PA1 forming an N type polycrystalline silicon film of a predetermined impurity concentration on the entire surface of semiconductor substrate, the N type polycrystalline silicon film having projecting and recessing parts in an upper surface thereof; PA1 forming a predetermined polycrystalline silicon film pattern by patterning the polycrystalline film with a first photoresist film pattern; PA1 forming an arsenic ion implanted layer by implanting arsenic ions in parallel with a normal to the surface of the semiconductor substrate using the first photoresist film pattern as a mask; PA1 forming drain and source regions composed of N+ type diffusion layers on the surface of the semiconductor substrate by removing the first photoresist film pattern and performing a heat treatment at a specified temperature so as to activate the arsenic ion implanted layer; PA1 forming a side wall oxide film on a side face of the polycrystalline silicon film pattern by depositing an oxide film on the entire surface of the semiconductor substrate and performing anisotropic etching; PA1 forming oxide films on the drain and source regions of the semiconductor substrate surface by thermal oxidation; PA1 forming a control gate electrode composed of a conductive film and a floating gate electrode composed of the polycrystalline silicon film pattern by forming the conductive film on the entire surface of the semiconductor substrate and sequentially patterning the conductive film, the gate insulating film and the polycrystalline silicon film pattern; and PA1 forming an interlayer insulating film on the entire surface of the semiconductor substrate, a contact hole reaching the N+ type diffusion layer in the interlayer insulating film and bit and source lines respectively connected to the drain and source regions through the contact hole on the surface of the interlayer insulating film. PA1 forming a gate oxide film in an element formation region of a semiconductor substrate surface by-thermal oxidation; PA1 forming an N type polycrystalline silicon film of a predetermined impurity concentration on the entire surface of the silicon substrate, the N type polycrystalline silicon film having projecting and recessing parts in an upper surface thereof; PA1 forming a specified polycrystalline silicon film pattern by patterning the polycrystalline silicon film with a first photoresist film pattern; PA1 forming a second photoresist film pattern covering at least a region planned for source formation, the second photoresist film pattern having an opening part in a region planned for drain formation; PA1 forming a second arsenic ion implanted layer in the semiconductor substrate by implanting arsenic ions of a quantity to form a first high impurity concentration region by first implanting energy in parallel with a normal to the surface of the semiconductor substrate using the second photoresist film pattern as a mask; PA1 forming a drain region composed of a first N+ type diffusion layer on the surface of the semiconductor substrate by removing the second photoresist film pattern and performing a first heat treatment at a specified temperature so as to activate the second arsenic ion implanted layer; PA1 forming a side wall oxide film on the side face of the polycrystalline silicon film pattern by depositing an oxide film on the entire surface of the semiconductor substrate and performing anisotropic etching; PA1 forming a third photoresist film pattern covering at least a region planned for drain formation, the third photoresist film pattern having an opening in a region planned for source formation; PA1 forming a third arsenic ion implanted layer in the semiconductor substrate by implanting arsenic ions of a quantity to form a second high impurity concentration region by second implanting energy in parallel with a normal to the surface of the semiconductor substrate using the third photoresist film pattern as a mask; PA1 forming a source region composed of a second N+ type diffusion layer on the surface of the semiconductor substrate by forming an oxide film on the surface of the semiconductor substrate by a thermal oxidizing method; PA1 eliminating the third photoresist film pattern and activating the third arsenic ion implanted layer; PA1 forming a control gate electrode composed of a conductive film and a floating gate electrode composed of the polycrystalline silicon film pattern by sequentially forming a gate insulating film and the conductive film on the entire surface of the semiconductor substrate and patterning the conductive film, the gate insulating film and the polycrystalline silicon film pattern; and PA1 forming a interlayer insulating film on the entire surface of the semiconductor substrate, a contact hole reaching the N+ type diffusion layer in the interlayer insulating film and the bit and source lines respectively connected to the drain and source regions through the contact hole on the surface of the interlayer insulating film.
From the above-noted formula, it should be understood that when a certain voltage is applied to the control gate, a voltage applied between the floating gate electrode and the P type silicon substrate is a value obtained by multiplying the voltage applied to the control gate electrode by a capacitance ratio.
For writing and erasing operations in the conventional memory cell described above, an FN tunneling phenomenon is utilized. By this method, compared with, for instance a channel hot electron injecting method, the consumption of currents during writing and erasing can be reduced more. Accordingly, the method is suited for reducing of a power supply voltage, which has been demanded of the flash memory in recent years.
However, in order to perform writing and erasing by using the FN tunneling phenomenon, it is necessary to apply a high electric field to the gate oxide film. In other words, if a capacitance ratio is taken into consideration, a higher voltage must be applied to the control gate electrode. Here, in order to generate a high voltage inside a chip, a dedicated circuit is necessary, and thus as a voltage is higher, an area occupied by the circuit in the chip is larger. In order to reduce the chip area, a voltage applied to the control gate electrode must be reduced as much as possible. Accordingly, it is necessary to set the capacitance ratio of the memory cell to a high level and increase an electric field applied to the gate oxide film when an FN tunneling phenomenon occurs.